A read-only memory (ROM) is a nonvolatile memory where information is permanently stored therein. Among semiconductor memory devices, Mask ROM devices are characterized in that information programmed in a memory cell is not erasable, nor is capable of storing new information in a specific cell. The Mask ROMs with buried bit lines (so called “flat cell”) are the most popular types of Mask ROMs. The term “mask” used here is due to a mask is introduced in order to define the digital information. Typically, an ion implantation process is used to adjust the threshold voltage to define the digital state of the memory cell. No dramatic modification is required by the manufacturing process to code (or to program) the digital information into the devices. Conventionally, the buried bit lines are formed by doping impurities into the substrate through a bit line mask. After the MOSFET devices are manufactured, one set of mask is needed for coding purposes. Therefore, the mask ROM device maybe made except the coding procedure prior to the placement of order from the clients. After the confirmation of the order from the clients, the information can be coded into devices according to the coding mask, thereby reducing the turn-around time. The coding of the device can be processed soon after an order is placed to move up the delivery/shipping date.
There are certain limitations in the conventional scheme of the coding procedure. The limitation for the programming types includes:
1. Diffusion programming, the diffusion programming step needs longer turn-around-time due to the coding by diffusion programming is determined prior to the manufacture procedure of the MOSFET devices.
2. Implantation programming, the procedure will be introduced in the middle stage of the manufacturing. The implantation coding is performed right after the formation of the MOSFETS but prior to the backend processes, such as interconnections and metallization. Ions are implanted into the channel region of MOSFETs during the implantation programming to alter their threshold voltages. The turn-around-time of such MASK ROM is shorter, which is accepted by current industries. However, the scheme needs additional mask to achieve the purpose, thereby increasing the cost and making the process becomes complicated.
3. Contact/via programming, in this scheme, a contact/via hole is formed on the source/drain contact nodes of the MOSFETs. Contact/via plugs are provided to connect the source/drain contact nodes of the MOSFETs for determining the on/off status of the MOS. The programming procedure becomes a later step in the scheme, thereby achieving the shortest turn-around-time. However, the scheme needs more layout space for forming the contact/via hole in a dielectric. Therefore, the method will increase the layout area of the cell. It conflicts the scaling-down trend and increases the manufacture cost.
The consideration of the mass production for the MASK ROM is not only the turn-around-time but also the size of the cell device. According to the previous arts, there is a need to further improve the conventional scheme.
One of the prior methods is described in FIGS. 1A–1C. Please refer to FIG. 1A, an isolation 102 is formed in the semiconductor substrate 101 having MOS formed thereon to act memory cell. The memory cell includes gate 103 and source/drain 104. The isolation can be constructed by the STI (shallow trench isolation) or by field oxide using LOCOS procedure. The gate is typically formed of polysilicon, source and drain can be p+ or n+ diffusion regions. In FIG. 1A, the source/drain is n+ diffusion region.
Turing to FIG. 1B, a lithography procedure is introduced with a coding mask to create photo-resist pattern 105 on a portion of the gate 103 and source/drain 104. If the gate of the MOS is exposed by the photo-resist pattern 105, the cell will be defined as digital “one” by subsequent ion implantation into the channel. On the contrary, the cell covered by the pattern 105 will be the digital “zero”.
Referring to FIG. 1C, a channel implantation is performed using the photo-resist pattern 105 as a mask to implant dopants into the uncovered cell, thereby coding the digital status in each individual cell, respectively. The following steps includes (a) the formation of isolation such as BPSG formation, (b) metallization, (c) inter-metal dielectric layer formation, (d) via formation and (e) the second metallization, the final passivation and so on.
After the placement of order, the coding mask is manufactured according to the client's coding specifications. Then, the lithography and coding step are subsequently performed to complete the programming in accordance with the specifications of the client. In the conventional scheme, one cell stores one digital status such as “one” or “zero”. Thus, the quantity of the information is determined by the number of the MOSFETs.